1. Technical Field
Embodiments of the present invention relate to a semiconductor memory apparatus, and more particularly, to an on-die termination circuit of a semiconductor memory apparatus.
2. Related Art
In general, when signals transmitted through a bus line having a predetermined impedance are input to another bus line having a different impedance, a signal loss occurs. Therefore, impedance matching between the two bus lines is needed to reduce the signal loss, which is referred to as on-die termination.
As shown in FIG. 1, an on-die termination apparatus according to the related art includes: an ODT input driver 10 that divides a power supply voltage VDDQ at a resistance ratio corresponding to a first code Pcode<0:N> and outputs a first line voltage P_out; a first comparator 20 that compares the first line voltage P_out with a reference voltage Vref according to a first code adjustment enable signal P_en and outputs a first comparison signal Pcmp_out; a first register 30 that counts the first code Pcode<0:N> according to the first comparison signal Pcmp_out; an ODT output driver 40 that divides the power supply voltage VDDQ at a resistance ratio corresponding to a second code Ncode<0:N> and outputs a second line voltage N_out; a second comparator 50 that compares the second line voltage N_out with the reference voltage Vref according to a second code adjustment enable signal N_en and outputs a second comparison signal Ncmp_out; and a second register 60 that counts the second code Ncode<0:N> according to the second comparison signal Ncmp_out. The ODT input driver 10 is modeled in the same manner as that in which a data input driver is modeled. The ODT output driver 40 is modeled in the same manner as that in which a data output driver is modeled.
Next, a code adjusting process according to the related art will be described below.
A process for adjusting the first code Pcode<0:N> and a process for adjusting the second code Ncode<0:N> may be performed at the same time, or they may be performed sequentially.
The process for adjusting the first code Pcode<0:N> is performed as follows.
The first code Pcode<0:N> having a predetermined value set by the first register 30 is input to the ODT input driver 10.
The ODT input driver 10 divides the power supply voltage VDDQ at a resistance ratio of resistors that are connected according to the first code Pcode<0:N> and a line impedance detecting resistor and outputs the first line voltage P_out.
The first comparator 20 compares the first line voltage P_out and the reference voltage Vref according to the first code adjustment enable signal P_en and outputs the first comparison signal Pcmp_out.
The first register 30 counts the first code Pcode<0:N> according to the first comparison signal Pcmp_out.
The ODT input driver 10 feeds back the first line voltage P_out corresponding to the counted first code Pcode<0:N> to the first comparator 20.
The first comparator 20 receives the first line voltage P_out and repeatedly performs the comparing operation and an operation for outputting the first comparison signal Pcmp_out.
The first code adjustment enable signal P_en is inactivated after a predetermined time.
When the first code adjustment enable signal P_en is inactivated, the first comparator 20 and the first register 30 stop, and at that time, the first code Pcode<0:N> is stored.
The process for adjusting the second code Ncode<0:N> is performed as follows.
An initial first code Ncode<0:N> set by the second register 60 is input to the ODT output driver 40.
The ODT output driver 40 divides the power supply voltage VDDQ at a resistance ratio of resistors that are connected according to the first and second codes Pcode<0:N> and Ncode<0:N> and outputs a second line voltage N_out.
The second comparator 50 compares the second line voltage N_out and the reference voltage Vref according to the second code adjustment enable signal N_en and outputs the second comparison signal Ncmp_out.
The second register 60 counts the second code Ncode<0:N> according to the second comparison signal Ncmp_out.
The ODT output driver 40 feeds back the second line voltage N_out corresponding to the counted second code Ncode<0:N> to the second comparator 50. The second comparator 50 repeatedly performs the comparing operation and an operation for outputting the second comparison signal Ncmp_out according to the second line voltage N_out.
The second code adjustment enable signal N_en is inactivated after a predetermined time.
When the second code adjustment enable signal N_en is inactivated, the second comparator 50 and the second register 60 stop, and at that time, the second code Ncode<0:N> is stored.
In the related art, when the reference voltage Vref is higher than the first line voltage P_out and the second line voltage N_out during the adjustment of the first and second codes Pcode<0:N> and Ncode<0:N>, the resistance value should increase. When the resistance value increases, the first code Pcode<0:N> increases, but the second code Ncode<0:N> decreases.
The first line voltage P_out and the second line voltage N_out may be considerably higher than the reference voltage Vref due to external and internal factors of the semiconductor memory apparatus. For example, when an external resistor is not connected to an external resistor connecting pin, a high impedance is generated.
When the first line voltage P_out and the second line voltage N_out are considerably higher than the reference voltage Vref, the first code Pcode<0:N> is continuously increased to reach a maximum value. As a result, the resistance value becomes infinity. Similarly, the second code Ncode<0:N> is continuously decreased to reach a minimum value. As a result, the resistance value becomes infinity.
The on-die termination circuit of the semiconductor memory apparatus according to the related art has a problem in that a code adjustment error occurs in which the first code Pcode<0:N> is adjusted to the maximum value and the second code Ncode<0:N> is adjusted to the minimum value, so that the resistance value becomes infinity, which makes it difficult to normally input and output data.